1. Field of the Invention
The present invention relates to electronic devices and, in particular, relates to devices and methods of forming capacitors for integrated circuitry.
2. Description of the Related Art
Since the introduction of the digital computer, electronic storage devices have been a vital resource for the retention of binary data. Conventional semiconductor electronic storage devices typically incorporate capacitor and transistor type structures, which are referred to as Dynamic Random Access Memory (DRAM), that temporarily store binary data based on the charged state of the capacitor structure. In general, this type of semiconductor Random Access Memory (RAM) often requires densely packed capacitor structures that are easily accessible for electrical interconnection therewith. Many of these capacitor structures are fabricated with layers of material including semiconductor, dielectric, and metal.
Some conventional capacitor structures have lower electrodes that are fabricated by first forning sacrificial spacers within a recessed substrate such that the capacitor occupies less than the width of the recess formed in the substrate. Conventional fabrication techniques of the lower electrode are complex and often requires many process steps. Typical process steps often require etching of a recess in a substrate, contiguous deposition of a sacrificial material layer on the substrate and within the recess, and etching of the sacrificial material layer so as to form sacrificial spacers on the sidewalls of the recess. Unfortunately, these sacrificial spacers reduce the width of the recess, which also reduces the effective width of the capacitor structure. Further processing steps require contiguous deposition of conductive material on the substrate and within the recess so as to overlie the sacrificial spacers, planar etching of the conductive layer to the substrate surface so as to form the lower electrode, and etching away of the sacrificial spacers so as to form cavities between the lower electrode and the substrate. Then, to form the rest of the capacitor structure, the dielectric layer followed by the top conductive layer can be deposited on the lower electrode.
Due to the excessive process steps involved with the use and formation of sacrificial spacers, inefficiencies can arise through the use of sacrificial spacers, which can inadvertently increase fabrication costs due the excessive process times, procedures, and materials. Another problem with using sacrificial spacers is that the capacitor structure including the lower electrode cannot use the full width of the recess, which can adversely affect the performance of the capacitor structure. Hence, there currently exists a need to reduce manufacturing costs associated with fabricating capacitor structures by simplifying inefficient procedures. To this end, there also exists a need to increase fabrication efficiency by improving the processing techniques associated with fabricating capacitor structures.
The aforementioned needs may be satisfied by a method of forming a capacitor structure on a substrate of the present teachings. In one embodiment, the method may comprise forming a recess in the substrate, positioning a first conductive layer on the substrate so as to overlie the substrate and the recess, and contouring the first conductive layer so as to define a lower electrode within the recess. In addition, the method may further comprise exposing the substrate and the lower electrode to an etchant, wherein the etchant diffuses through the lower electrode and etches the substrate away from the lower electrode to thereby at least partially isolate the lower electrode. Moreover, the method may still further comprise depositing a dielectric layer on the isolated lower electrode and depositing a second conductive layer on the dielectric layer so as to form an upper electrode.
In one aspect, the method may still further comprise depositing an insulation layer on the second conductive layer. In addition, forming a recess in the substrate may include etching a recess in the substrate so as to define a cell container having a recessed interior field region. Also, positioning a first conductive layer may include depositing a thin layer of conductive material, wherein depositing a thin layer of conductive material may include depositing a conductive layer to at least greater than approximately 150 A. Moreover, positioning a first conductive layer may include depositing a permeable layer of conductive material. Also, positioning a first conductive layer may include depositing a first conductive material selected from the group consisting of a metal, metal alloy, and a semiconductor including polysilicon, TiN, and WSi. In another aspect, contouring the first conductive layer may include planar etching the first conductive layer down to the substrate. In addition, exposing the substrate and the lower electrode to an etchant may include exposing the substrate and the lower electrode to HF. Also, depositing a dielectric layer may include depositing a dielectric material selected from the group consisting of Aluminum-Oxide (Al2O3) and Hafnium-Oxide (HfO3). Moreover, depositing the second conductive layer may include depositing a second conductive material selected from the group consisting of a metal, metal alloy, and a semiconductor including polysilicon, TiN, and WSi.
The aforementioned needs may also be satisfied by a method of forming a plurality of capacitor structures on a substrate. In one embodiment, the method may comprise forming a plurality of recesses in the substrate, depositing a first conductive layer on the substrate so as to overlie the plurality of recesses, and defining a plurality of lower electrodes within the recesses formed in the substrate by removing at least a portion of the first conductive layer. In addition, the method may further comprise treating the substrate through the lower electrodes to thereby remove at least a portion of the substrate to thereby at least partially isolate the lower electrodes, depositing a dielectric layer on the isolated lower electrodes, and depositing a second conductive layer on the dielectric layer so as to form an upper electrode.
The aforementioned needs may also be satisfied by a method of forming a plurality of capacitor structures on a substrate. In one embodiment, the method may comprise forming a plurality of recesses in the substrate a first distance apart so as to define a common region therebetween, depositing a first conformal layer of conductive material on the substrate so as to overlie the substrate and the recess, and removing at least a portion of the first conformal layer so as to define a plurality of lower electrodes within the recesses. In addition, the method may further comprise exposing the substrate and lower electrodes to an etchant selected to remove at least a portion of the substrate surrounding the lower electrodes including the common region between the lower electrodes to thereby at least partially isolate the lower electrodes. Moreover, the method may still further comprise depositing a conformal dielectric layer on the isolated lower electrode and depositing a second conformal layer of conductive material on the dielectric layer so as to form an upper electrode.
The aforementioned needs may also be satisfied by a capacitor device formed on a substrate. In one embodiment, the device may comprise a lower electrode having permeable sidewalls that allow an etchant to diffuse therethrough so as to etch back at least a portion of the substrate therefrom, a dielectric layer formed on the lower electrode, and an upper electrode formed on the dielectric layer. In one aspect, the lower electrode may comprise a semiconductor material, the dielectric layer may comprise an insulation material, and the upper electrode may comprise a metal material to thereby form an MIS capacitor device. In another aspect, the lower electrode may comprise a metal material, the dielectric layer may comprise an insulation material, and the upper electrode may comprise a metal material to thereby form an MIM capacitor device. In still another aspect, the lower electrode may comprise a semiconductor material, the dielectric layer may comprise an insulation material, and the upper electrode may comprise a semiconductor material to thereby form an SIS capacitor device. These and other objects and advantages of the present teachings will become more fully apparent from the following description taken in conjunction with the accompanying drawings.